Rising and Falling Edge Detector using Verilog

 In the real word, there might be many scenario that we need to detect rising edge or falling edge of the signal. If rising/falling edge happens on particular signal, then design can perform certain task. This rising or falling edge can be detected using following code. This code is done in Verilog language. In given below example code, clock clk, input signal sig_a, output rising edge signal ris_a and falling edge signal fal_a are defined. Both ris_a and fal_a are high for one clock cycle when circuit detects rising or falling edge on the sig_a respectively.

Excitation and Characteristic Table of SR Flip Flop

The basic SR Flip-Flop is shown below. The inputs, labeled S and R are used to SET and RESET the device, respectively. The outputs Q and Q’ are complementary. Because the Flip-Flop is unclocked, any change to the inputs will produce a change at the outputs. An invalid state occurs when both inputs are low; thus, the inputs should be kept high except when the Flip-Flop is to be set or cleared. Note that there are other implementations for a latch. Here we are showing a NAND implementation.

Number System in Digital Design

To represent something we require symbols and to represent count we require Numbers. Number System is very important in Digital Technology. The most commonly used number systems are Decimal(Base 10), Binary(Base 2), Hexadecimal(Base 16) and Octal(Base 8). We all are very much familiar with Decimal Number System.

Logic Gates in Digital World

Logic gates are basic building blocks of any digital circuits. Logic gates are electronics device that gives output on the different combinations of digital inputs. Different Logic gates are constructed using different technologies depending on different Logic Family like TTL, CMOS, DTL, ECL etc. Logic Circuits include devices such as multiplexers, registers, memory units, processors, which contains more than 100 millions Logic Gates.

There are total six Logic Gates are available

1. AND Gate.
2. OR Gate.
3. NOT Gate.
4. NAND Gate.
5. NOR Gate.
6. EX-OR Gate.
7. EX-NOR Gate.

Implement Divide by 2, 4, 8 and 16 Counter using Flip-Flop

Counter plays a very important role into chip designing and verification. It is a very essential part of the VLSI Domain. Whenever we want to design or verify our design, most of the time we require slowing down frequencies. We can suppress this frequency using this counter by 2, 4, 8 or 16 times. Here circuit diagram and verilog code are given below.

Setup Time and Hold Time

These two parameters are associated with Flip-Flop. Setup Time and Hold Time are two most important factors in Synchronous Design in VLSI Domain. If either of them is violated then Flip-Flop will not give proper output. 

Setup Time: - It’s a time interval before the Clock signal is triggered, where Data signal should be stable. So, that Data is easily sampled by the Flip-Flop.

Difference between Flip-Flop and Latch

Flip-Flop	Latch
Flip-Flop is Edge sensitive device.	Latch is Level sensitive device.
In Flip-Flop, output will change on rising or falling edge of clock signal.	In Latch, if Enable/Clock signal is high then output will change accordingly input.
So, we can say that Flip-Flop is a Synchronous version of Latch.	So, we can say that Latch is Asynchronous device.
Flip-Flop based design creates less timing problems.	Latch based design creates more timing problems.
In design Flip-Flop takes more area compared to Latch.	In design Latch takes less area compared to Flip-Flop.
In design Flip-Flop consumes more power compare to Latch.	In design Latch consumes less power compare to Flip-Flop.

Implement XOR Gate using 2x1 Multiplexer

We have two inputs A, B. Connect one of Multiplexer's input to input 'B'. Connect input 'B' to input of NOT gate and output of this NOT gate connect to second input of Multiplexer. Then connect input 'A' to selection line of Multiplexer. So, this Multiplexer will XORing operation of input A, B.

Implement OR Gate using 2x1 Multiplexer

We have two inputs A, B. Connect one of Mux's input to logic '1' and second to input 'B'. Connect input 'A' to selection line of Mux. So, output will give ORing operation of two inputs A, B.

Implement AND Gate using 2x1 Multiplexer

We have two inputs A, B. Connect one of Mux's input to logic '0' and second to input 'B'. Connect input A to selection line of Mux. So, output of Mux will give anding operation of two inputs A and B.

Implement BUFFER Gate using XOR Gate

Connect one of XOR gate's input to logic '0' and connect second to input 'a'. So XOR gate will give output as input.

Implement NOT Gate using XOR Gate

Connect one of XOR gate's input to logic 1 and connect second input to input 'a'. So output of XOR gate will give inverted output of input.