Verilog Code for 4-Bit Sequential Multiplier

Sr. No.	Name of the Pin	Direction	Width	Description
1	a	Input	4	Data Input
2	b	Input	4	Data Input
3	Load	Input	1	Load Input
4	Rst_a	Input	1	Reset Input
5	Clk	Input	1	Clock Input
6	Op	Output	8	Multiplied Output
7	Ready_out	Output	1	Ready_out Output

Sequential multiplier multiplies two inputs of four bits and gives output of eight bits. It also gives ready_out signal. It will give output in single cycle. It accepts data of a and b when load signal is high. If load signal is low, then it will not accept the data and output will not generated. It will generate multiplied output and ready_out signal high. 

module seq_multi_4b(op,ready_out,a,b,load,clk,rst_a);
output reg [7:0] op;
output reg ready_out;
input [3:0] a,b;
input load,clk,rst_a;
reg [7:0] tmp0,tmp1,tmp2,tmp3;

wire [7:0] tmp;

assign tmp={4'b0000,b};

   always @(posedge rst_a,posedge clk)
   
     begin 
 if (rst_a)
   begin
      op=8'bzzzz_zzzz;
      ready_out=1'bz;
   end
 else
   if (load)
     begin
        case (a[0])
          1'b0:tmp0=8'b0000_0000;
          1'b1:tmp0=tmp;
        endcase
        case (a[1])
          1'b0:tmp1=8'b0000_0000;
          1'b1:tmp1=tmp<<1;
        endcase
        case (a[2])
          1'b0:tmp2=8'b0000_0000;
          1'b1:tmp2=tmp<<2;
        endcase
        case (a[3])
          1'b0:tmp3=8'b0000_0000;
          1'b1:tmp3=tmp<<3;
        endcase
          op=tmp0+tmp1+tmp2+tmp3;
          ready_out=1'b1;
     end
 end
endmodule